1. Field of the Invention
The present invention relates to an electronic device package, and in particular relates to an electronic package fabricated by a wafer level package process.
2. Description of the Related Art
Through-silicon via (TSV package process) packaging techniques have been disclosed to package advanced electronic devices. However, difficulties still exist for fabricating TSV packaged electronic devices, as mass production yields are insufficient, when trying to obtain a conductive trace layer in a via of high aspect ratio.
FIG. 1 shows a partial plane view of a conventional electronic device package 1. A plurality of conductive contact pads 14 is disposed on a peripheral area 11 of a chip active area 10. A conventional TSV packaging process forms a corresponding via 12 at the position of each conductive contact pad 14. Each via 12 has a single contact hole 16 therein to expose one corresponding conductive contact pad 14.
However, the aspect ratios of via 12 are normally at least 1.6, such that subsequent filling processes for various material layers are difficult. Thus, an electronic device package and a fabrication method thereof which can overcome the fabrication problems of vias of high aspect ratios is therefore desired.